Super-Scalar Processor Design

A super-scalar processor is one that is capable of sustaining an instruction-execution rate of more than one instruction per clock cycle. Maintaining this execution rate is primarily a problem of scheduling processor resources (such as functional units) for high utilrzation. A number of scheduling algorithms have been published, with wide-ranging claims of performance over the single-instruction issue of a scalar processor. However, a number of these claims are based on idealizations or on special-purpose applications. This study uses trace-driven simulation to evaluate many different super-scalar hardware organizations. Super-scalar performance is limited caused by both branch delays and instruction misap rimarily b instruction-fetch inefficiencies rgnment. 8ecause of this instruction-fetch lirnitation, it is not worthwhile to explore highly-concurrent execution hardware, Rather, it is more appro riate to explore economical execution hardware that more closely matches the instructron tLoughput provided b reducing the instruction-fetch inefii the instruction fetcher. This stud ciencies and explores the resulting iI examines techniques for ardware organizatrons. This study concludes that a super-scalar processor can have nearly twice the scalar processor, but that this re uires 1 that four major hardware features: p” xformance of a out-o -order execution, register renarmng, branch pre iction, and a four-instruction decoder. These features are interdependent, and removing any single feature reduces average performance by 18% or more. However, there are many hardware simplifications that cause only a small performance reduction.